This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-347540, filed Nov. 15, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device having a memory cell array with a MOS structure formed in a well region formed on a semiconductor substrate, and, more particularly to a semiconductor memory device in which a memory cell array is divided into a plurality of blocks, and a memory content can be rewritten or erased with one block as a unit.
2. Description of the Related Art
Conventionally there is available a non-volatile semiconductor memory device having a structure disclosed in, for example, a Jpn. Pat. Appln. KOKAI Publication No. 9-307005. This memory device is configured by using a non-volatile memory transistor with a MOS structure which is used as an EEPROM memory cell for electrically erasing/writing data. There will be explained a structure of this prior art non-volatile semiconductor memory device by referring to FIG. 7.
An example shown in FIG. 7 has a structure in which two P-type well regions 102A and 102B are formed in an N-type well region 101 formed on a P-type semiconductor substrate 100. Non-volatile semiconductor memory cells 103A and 103B having a MOS structure are formed on the P-type well regions 102A and 102B, respectively.
For example, one memory cell 103A is a memory cell with an NMOS structure which has a gate structure in which there are provided a floating gate 107A and a control gate 108A formed of two layer polycrystalline silicon film via an insulation film 106A. The memory cell 103A has a gate insulation film 105A formed on a surface of the P-type well 102A. A source 104A and a drain 109A of the memory cell transistor 103A are formed as N-type diffusion layers on the surface region of the P-type well 102A. The diffusion layers 104A and 109A are formed to sandwich the gate insulation film 105A there-between.
An actual semiconductor memory device has a structure in which a plurality of memory cells are arranged in a matrix manner on the P-type well 102A, and any of the memory cells is selected by selectively driving a plurality of row lines (WLi) connected to the control gate 108A of each memory cell and a plurality of column or bit lines (BLi) connected to the drain 109A.
With respect to the other P-type well 102B, the NMOS memory cell 103B is formed in a similar manner.
Here, there will be explained an operation of the memory cell 103A having a structure shown in FIG. 7. In a data erasure mode for erasing data stored in the floating gate 107A, a high voltage of, for example, 10V is applied to the source 104A of the memory cell 103A, the N-type well 101 and the P-type well 102A. Further, a voltage of, for example, xe2x88x927V is applied to the row line WLi, and xe2x88x927V is applied to the control gate 108A of all memory cells formed on the P-type well 102A. Furthermore, the drain 109A is in the floating state.
At this time, electrons trapped in the floating gate 107A are discharged to a channel region formed between the source 104A and the drain 109A in the vicinity of the surface of the P-type well 102A with the FN tunneling of the gate insulation film 105A. At this time, a threshold of the memory cell 103A is lowered (the data state at this time is set to xe2x80x9c1xe2x80x9d).
Next, data writing will be explained. In the data writing, for example, the memory cell 103A is selected for data writing so that any one of the plurality of row lines WLi is set to, for example, 9V while one or more of the plurality of bit lines BLi are set to, for example, 5V. The source 104A potential and the N-type well 101 potential are 0V. Assuming that the memory cell 103A is selected at this time, electrons are injected to the floating gate 107A with hot electron injection. At this time, the threshold of the memory cell 103A becomes high (the data state at this time is set to xe2x80x9c0xe2x80x9d.)
Next, data reading will be explained. For example, any of the plurality of row lines WLi is set to, for example, about 5V in order select the memory cell 103A for reading. Furthermore, any of the bit lines BLi is set to a low voltage, for example, about 0.7V. Furthermore, the source potential and the N-type well 101 potential is 0V.
When the selected memory cell 103A is set to xe2x80x9c0xe2x80x9d namely, in a data written state at this time, the memory cell 103A is not turned on, therefore no current flows. Furthermore, when the selected memory cell 103A is set to xe2x80x9c1xe2x80x9d, namely in the erasure state, the memory cell 103A is turned on, then a cell current, for example, current on the order of, for example, 40 xcexcA is allowed to flow. The amplitude of this current is amplified by a sense amplifying circuit (not shown) or the like to be read.
In this manner, in the prior art structure of FIG. 7, the source potential SLi and the potential of the N-type well 101 are independently set. When even a slight time difference is present in the operation of setting these potentials, and the P-type well 102A to which the source line SLi potential is supplied has a positive potential with respect to the N-type well 101 to which an N-type well potential is supplied, a forward direction bias is applied to a PN junction between the P-type well 102A and the N-type well 101. As a consequence, there is a fear that a normal operation of a semiconductor memory device is hindered and the forward direction current flows in the PN junction so that too much power is consumed.
According to one aspect of the present invention, there is configured a semiconductor memory device, comprising:
a semiconductor substrate of a first conductive type;
a first well region of a second conductive type formed on the semiconductor substrate;
a second well region of a first conductive type formed in the first well region;
a third well region of a first conductive type formed in the first well region;
a memory cell array which is formed on each of the second well region and the third well region and which has a plurality of memory cells with a MOS structure;
a first decoding circuit for selectively supplying a rewriting voltage signal to the second well region and a source region of the memory cell at the time of rewriting data of the memory cell array; and
a second decoding circuit for selectively supplying the rewriting voltage signal to the first well region.